DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

Ghislain Fraidy Bouesse (1) , Marc Renaudin (1) , S. Dumont (1) , F. Germain (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 DCSSI/SDS/LTI - Laboratoire des Technologies de l'Information

The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.

Mots clés: differential-power-analysis; quasi-delay-insensitive-asynchronous-circuits; design-flow; electrical-signature

Domaines: Architectures Matérielles [cs.AR]; Electronique

Ghislain Fraidy Bouesse, Marc Renaudin, S. Dumont, F. Germain. DPA on quasi delay insensitive asynchronous circuits: formalization and improvement. DATE'05, Mar 2005, Munich, Germany. pp.424 - 429, ⟨10.1109/DATE.2005.124⟩. ⟨hal-00009567⟩