Hardware Transactions in Nonvolatile Memory

Hillel Avni (1) , Eliezer Levy (1) , Avi Mendelson (2)

1 ERI - Huawei Technologies European Research Center
2 Technion - Israel Institute of Technology [Haifa]

Hardware transactional memory (HTM) implementations already provide a transactional abstraction at HW speed in multi-core systems. The imminent availability of mature byte-addressable, nonvolatile memory (NVM) will provide persistence at the speed of accessing main memory. This paper presents the notion of persistent HTM (PHTM), which combines HTM and NVM and features hardware-assisted, lock-free, full ACID transactions. For atomicity and isolation, PHTM is based on the current implementations of HTM. For durability, PHTM adds the algorithmic and minimal HW enhancements needed due to the incorporation of NVM. The paper compares the performance of an implementation of PHTM (that emulates NVM aspects) with other schemes that are based on HTM and STM. The results clearly indicate the advantage of PHTM in reads, as they are served directly from the cache without locking or versioning. In particular, PHTM is an order of magnitude faster than the best persistent STM on read-dominant workloads.

Domains: Distributed, Parallel, and Cluster Computing [cs.DC]

Hillel Avni, Eliezer Levy, Avi Mendelson. Hardware Transactions in Nonvolatile Memory. DISC 2015, Toshimitsu Masuzawa; Koichi Wada, Oct 2015, Tokyo, Japan. ⟨10.1007/978-3-662-48653-5_41⟩. ⟨hal-01207244⟩