Highly configurable place and route for analog and mixed-signal circuits

Abstract : —Analog design remains a manual task because of the complexity of the interations among devices. Automation tools dedicated to analog circuits are not as mature as the digital automation tool but have been improved a lot, at a point that they can help at individual steps in the analog design flow. This Ph. D. thesis is oriented toward creating a semi-automated mixed design flow controlled by the designer with a particular focus on an analog and mixed signal placer and router. The results show the ability of our tool at generating multiple placed and routed layouts respecting designer's constraints. I. CONTEXT AND MOTIVATIONS An automatic place and route tool should produce analog device-level layouts similar in density and performance to the high-quality manual layouts. To achieve this task, the capability to deal with layout constraints, in order to decrease unwanted parasitics due to the process variations, is mandatory [1]. Recent research focused on using simulated annealing algorithm [2] in combination with topological representations to respect these analog constraints. Topological representations encode the positioning relations between devices and the optimizer alters their relative positions. The most popular representations are Sequence-Pair [3], B*-Tree [4], Transitive Closure Graph [5], Ordered-Tree [6] and slicing floorplans [7] and they are coupled with some constraints to respect at the same time. Although most of the recent works focus on highly automated approaches based on optimization processes [8], we believe that giving more control to designers and using their interventions to set some constraints is mandatory to get resulting layouts accepted by designers. Our semi-automatic approach also helps designers to debug more efficiently and makes adjustments easier while some tiresome and error-prone tasks are automated. II. ANALOG PLACEMENT Digital and analog circuits have a dedicated area on a system-on-chip circuit so they can be independently designed within a specific space (fig. 1). It is also common to design analog circuit in rows of devices where the height of each row of devices should be adjustable so it can match its dedicated area. In order to organize devices in row, we use the slicing tree structure which will be specified by designers. Having designers defining the slicing tree, it means they will have control over the global topological Fig. 1. Mixed signal circuit floorplanning and analog placement in 3 rows placement. Their choice will impact on analog placement constraints such as promixity range, signal path and regularity. To set rows of devices, the height of each device needs to be similar and to do so, designers have to consider possible aspect ratios for each device by varying their number of fingers. In a bottom-up propagation manner, designers will have choices of multiple placements' results ordered according to their total aspect ratio. Designers also have control over margin tolerances which can eliminate some placements if devices' height in a row are too different. Fig. 2. Circuits possible dimensions graph Once designers define their slicing tree and the previously mentioned constraints, our placer will process the accepted placements in a few seconds and present them on an interactive graph (fig. 2). Each point of the graph represents a valid placement and its coordinates are its width and height. A point can be selected and our placer will generate, in less than a second, the according placement. Designers can pick the most appropriate placement based on his experiences and the aspect ratio of the floorplan. III. ANALOG AND MIXED SIGNAL ROUTING Once the placement phase is performed with the slicing tree, it is then used for the routing phase. The purpose of this work is to place and route mixed signal circuits, this is the reason why our router has been built through a common
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Eric Lao, Marie-Minerve Louërat, Jean-Paul Chaput. Highly configurable place and route for analog and mixed-signal circuits. PhD Forum at Design, Automation and Test in Europe Conference (DATE), Mar 2017, Lausanne, Switzerland. ⟨hal-01689918⟩

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