Using binary decision diagrams to speed up the test pattern generation of behavioral circuit descriptions written in hardware description languages

Loic Vandevanter (1) , Jean-François Santucci (2)

1 EERIE
2 SPE - Sciences pour l'environnement

In this paper, we focus on test pattern generation for circuit descriptions written in hardware description languages according to the circuit behavior. We develop an algorithmic improvement method which is devoted to speed up the deterministic and fault-oriented test systems which deal with such circuit descriptions. The improvement method is implemented and inserted in a behavioral test pattern generator in order to be validated. Experimental results have been obtained which show the efficiency of our approach

Domaines: Modélisation et simulation; Micro et nanotechnologies/Microélectronique

Loic Vandevanter, Jean-François Santucci. Using binary decision diagrams to speed up the test pattern generation of behavioral circuit descriptions written in hardware description languages. IEEE International Symposium on Circuits and Systems, 1994. ISCAS '94, 1994, London, United Kingdom. pp.279-282, ⟨10.1109/ISCAS.1994.408809⟩. ⟨hal-00177986⟩