Selective Hardening Methodology for Combinational Logic

Abstract :

Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is based on the SPRA algorithm for calculating logical masking, and it is capable to automatically perform a trade-off between reliability improvements and associated costs, providing a list of the most effective candidates for hardening. The methodology is applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that the methodology is able to diminish the unreliability of circuits in a cost-effective manner.

Type de document :
Communication dans un congrès
Latin-American Test Workshop, Apr 2012, Quito, Ecuador. pp.6, 2012
Liste complète des métadonnées

Littérature citée [16 références]  Voir  Masquer  Télécharger

https://hal-imt.archives-ouvertes.fr/hal-00695808
Contributeur : Admin Télécom Paristech <>
Soumis le : mercredi 9 mai 2012 - 21:33:37
Dernière modification le : jeudi 11 janvier 2018 - 06:23:39
Document(s) archivé(s) le : vendredi 30 novembre 2012 - 11:31:02

Fichier

latw_camera.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : hal-00695808, version 1

Citation

Samuel Nascimento Pagliarini, Lirida Alves de Barros Naviner, Jean-François Naviner. Selective Hardening Methodology for Combinational Logic. Latin-American Test Workshop, Apr 2012, Quito, Ecuador. pp.6, 2012. 〈hal-00695808〉

Partager

Métriques

Consultations de la notice

306

Téléchargements de fichiers

386