Skip to Main content Skip to Navigation
Conference papers

An Efficient Hardware Architecture without Line Memories for Morphological Image Processing

Abstract : In this paper, we present a novel hardware architecture to, achieve erosion and dilation with a large structuring element. We are, proposing a modification of HGW algorithm with a block mirroring, scheme to ease the propagation and memory access and to minimize, memory consumption. It allows to suppress the needs for backward scan-, ning and gives the possibility for hardware architecture to process very, large lines with a low latency. It compares well with the Lemonnier's, architecture in terms of ASIC gates area and shows the interest of our, solution by dividing the circuit area by an average of 10.
Document type :
Conference papers
Complete list of metadata

Cited literature [8 references]  Display  Hide  Download

https://hal-mines-paristech.archives-ouvertes.fr/hal-00834012
Contributor : Bibliothèque Mines Paristech <>
Submitted on : Thursday, June 13, 2013 - 6:28:23 PM
Last modification on : Thursday, September 24, 2020 - 4:38:03 PM
Long-term archiving on: : Saturday, September 14, 2013 - 4:16:43 AM

File

HGWimproved.pdf
Files produced by the author(s)

Identifiers

Citation

Christophe Clienti, Michel Bilodeau, Serge Beucher. An Efficient Hardware Architecture without Line Memories for Morphological Image Processing. 10th International Conference on Advanced Concepts for Intelligent Vision Systems (ACIVS 2008), Oct 2008, Juan les Pins, France. pp.147-156, ⟨10.1007/978-3-540-88458-3_14⟩. ⟨hal-00834012⟩

Share

Metrics

Record views

727

Files downloads

527