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Conference papers
Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems
Etienne Borde
1, 2
Laurent Pautet
1, 2
Fabien Cadoret
1, 2
Smail Rahmoun
1, 2
Frank Singhoff
1
ACES - Autonomic and Critical Embedded Systems
LTCI - Laboratoire Traitement et Communication de l'Information
Etienne Borde 1, 2
Author IdHAL : etienne-borde
Laurent Pautet 1, 2
Author IdHAL : laurent-pautet
Fabien Cadoret 1, 2
Author
Smail Rahmoun 1, 2
Author
Frank Singhoff
Author
1
ACES - Autonomic and Critical Embedded Systems (46 rue Barrault
75013 Paris - France)
- LTCI - Laboratoire Traitement et Communication de l'Information (19 Place Marguerite Perey 91120 PALAISEAU - France)
- IMT - Institut Mines-Télécom [Paris] (37-39 Rue Dareau, 75014 Paris - France)
- Télécom Paris (19 Place Marguerite Perey 91120 Palaiseau - France)
2
INFRES - Département Informatique et Réseaux (46, rue Barrault
75013 Paris - France)
- Télécom ParisTech (46 rue Barrault 75634 Paris Cedex 13 - France)
Document type :
Conference papers
Complete list of metadatas
https://hal-imt.archives-ouvertes.fr/hal-01115723
Contributor : Admin Télécom Paristech <>
Submitted on : Wednesday, February 11, 2015 - 4:32:24 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:13 AM
Contributor : Admin Télécom Paristech <>
Submitted on : Wednesday, February 11, 2015 - 4:32:24 PM
Last modification on : Wednesday, September 30, 2020 - 8:54:13 AM
Identifiers
- HAL Id : hal-01115723, version 1
Citation
Etienne Borde, Laurent Pautet, Fabien Cadoret, Smail Rahmoun, Frank Singhoff. Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems. International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.44-50. ⟨hal-01115723⟩
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