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Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems

Etienne Borde 1, 2 Laurent Pautet 1, 2 Fabien Cadoret 1, 2 Smail Rahmoun 1, 2 Frank Singhoff 
1 ACES - Autonomic and Critical Embedded Systems
LTCI - Laboratoire Traitement et Communication de l'Information
2 INFRES - Département Informatique et Réseaux
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Conference papers
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https://hal-imt.archives-ouvertes.fr/hal-01115723
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Submitted on : Wednesday, February 11, 2015 - 4:32:24 PM
Last modification on : Tuesday, May 17, 2022 - 6:50:02 PM

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  • HAL Id : hal-01115723, version 1

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INSTITUT-TELECOM | PARISTECH | TDS-MACS | IRT-SYSTEMX | LTCI | INFRES | ACES

Citation

Etienne Borde, Laurent Pautet, Fabien Cadoret, Smail Rahmoun, Frank Singhoff. Architecture Models Refinement for Fine Grain Timing Analysis of Embedded Systems. International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.44-50. ⟨hal-01115723⟩

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