Automatic generation of hardware FIR filters from a frequency domain specification

Nicolas Brisebarre (1, 2) , Florent de Dinechin (3) , Silviu-Ioan Filip (2) , Matei Istoan (3)

1 LIP - Laboratoire de l'Informatique du Parallélisme
2 ARIC - Arithmetic and Computing
3 SOCRATE - Software and Cognitive radio for telecommunications

Digital filtering operations are a prime example of the flexibility and opportunities offered by solutions using reconfigurable hardware. This article proposes an efficient solution for the automatic design and synthesis of finite impulse response (FIR) filters targeting FPGAs. Based on a novel approach to the filter coefficient quantization problem, it produces results which are faithful to a high-level frequency-domain specification. An automated design process is also proposed where user intervention is limited to a very small number of relevant input parameters. Computing the optimal value of the other parameters not only simplifies the user interface. The resulting architectures also outperform those generated by mainstream tools in accuracy, performance, and resource consumption.

Mots clés: FPGA; FIR coefficient quantization

Domaines: Traitement du signal et de l'image [eess.SP]; Arithmétique des ordinateurs; Architectures Matérielles [cs.AR]

Nicolas Brisebarre, Florent de Dinechin, Silviu-Ioan Filip, Matei Istoan. Automatic generation of hardware FIR filters from a frequency domain specification. 2016. ⟨hal-01308377v1⟩